ADC12D040

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SNAS171E – JUNE 2002 – REVISED MARCH 2013

DC and Logic Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =

+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits

apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1)(2)(3)

Typical

Limits

Units

Symbol

Parameter

Conditions

(4)

(4)

(Limits)

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

VDR = 2.5V

2.3

V (min)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA

VDR = 3V

2.7

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA, VDR = 3V

0.4

V (max)

VOUT = 2.5V or 5V

100

nA

IOZ

TRI-STATE Output Current

VOUT = 0V

−100

nA

+ISC

Output Short Circuit Source Current

VOUT = 0V

−20

mA

−ISC

Output Short Circuit Sink Current

VOUT = VDR

20

mA

COUT

Digital Output Capacitance

5

pF

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, VREF = 2.0V

93

110

mA (max)

IA

Analog Supply Current

PD Pin = VDR

15

mA

PD Pin = DGND

16

18

mA (max)

ID

Digital Supply Current

PD Pin = VDR

0

mA

PD Pin = DGND, CL = 0 pF

(5)

10.5

12

mA (max)

IDR

Digital Output Supply Current

PD Pin = VDR

0

mA

PD Pin = DGND, CL = 0 pF

(6)

600

700

mW

Total Power Consumption

PD Pin = VDR

75

mW

Rejection of Full-Scale Error with

PSRR1

Power Supply Rejection

56

dB

VA = 4.75V vs. 5.25V

(5)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x

f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

(6)

Excludes IDR. See

(6).

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =

+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits

apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3) (4)

Typical

Limits

Units

Symbol

Parameter

Conditions

(5)

(5)

(Limits)

fCLK1

Maximum Clock Frequency

40

MHz (min)

fCLK2

Minimum Clock Frequency

100

kHz

tCH

Clock High Time

9

ns

tCL

Clock Low Time

9

ns

tCONV

Conversion Latency

6

Clock Cycles

tOD

Data Output Delay after Rising CLK Edge VDR = 3.0V

10

17.5

ns (max)

tAD

Aperture Delay

1.2

ns

tAJ

Aperture Jitter

2

ps rms

tHOLD

Clock Edge to Data Transition

8

ns

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited, see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above VA or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure

accurate conversions (see Figure 2).

(2)

To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.

(4)

Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.

(5)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average

Outgoing Quality Level).

Copyright © 2002–2013, Texas Instruments Incorporated

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