ADC12D040

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SNAS171E – JUNE 2002 – REVISED MARCH 2013

FUNCTIONAL DESCRIPTION

Operating on a single +5V supply, the ADC12D040 uses a pipeline architecture and has error correction circuitry

to help ensure maximum performance. The differential analog input signal is digitized to 12 bits and the reference

input is buffered to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 100 ksps (typical) and 40 Msps

with fully specified performance at 40 Msps. The analog input voltage for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 6 clock cycles. A choice of

Offset Binary or Two's Complement output format is selected with the OF pin.

A logic high on the power down (PD) pin reduces the converter power consumption to 75 mW.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12D040:

4.75V

≤ VA ≤ 5.25V

VD = VA

2.35V

≤ VDR ≤ VD

VREF/2 ≤ VCM ≤ VA - VREF

100 kHz

≤ fCLK ≤ 40 MHz

1.0V

≤ VREF ≤ 2.4V

Analog Inputs

The ADC12D040 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There

is one reference input pin, VREF.

The analog input circuitry contains an input boost circuit that provides improved linearity over a wide range of

analog input voltages. To prevent an on-chip over voltage condition that could impair device reliability, the input

signal should never exceed the voltage described as

VA - VREF/2.

(5)

Reference Pins

The ADC12D040 is designed to operate with a 2.0V reference, but performs well with reference voltages in the

range of 1.0V to 2.4V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12D040.

Increasing the reference voltage (and the input signal swing) beyond 2.4V may degrade THD for a full-scale input

especially at higher input frequencies. It is important that all grounds associated with the reference voltage and

the input signal make connection to the analog ground plane at a single point in that plane to minimize the

effects of noise currents in the ground path.

The ADC12040 will perform well with reference voltages up to 2.4V for full-scale input frequencies up to 10 MHz.

However, more headroom is needed as the input frequency increases, so the maximum reference voltage (and

input swing) will decrease for higher full-scale input frequencies.

The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass

purposes. These pins should each be bypassed to ground with a 0.1 µF capacitor. Smaller capacitor values will

allow faster recovery from the power down mode, but may result in degraded noise performance. DO NOT LOAD

these pins. Loading any of these pins may result in performance degradation.

The nominal voltages for the reference bypass pins are as follows:

VRMA = VRMB = VA / 2

VRPA = VRPB = VRM + VREF / 2

VRNA = VRNB = VRM − VREF / 2

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Product Folder Links: ADC12D040