ADC12D040

SNAS171E – JUNE 2002 – REVISED MARCH 2013

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Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-

STATE outputs of the ADC12L066 to drive a bus. Rather, each output pin should be located close to and drive a

single digital input pin. To further reduce ADC noise, a 100

Ω resistor in series with each ADC digital output pin,

located close to their respective pins, should be added to the circuit.

The PD Pin

The PD pin, when high, holds the ADC12D040 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 75 mW with a 40 MHz clock and 40mW if the clock is

stopped when PD is high. The output data pins are undefined in the power down mode and the data in the

pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 4, 5, 6, 12, 13 and

14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry

before conversions can be accurate. Smaller capacitor values allow faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

The OF Pin

The output data format is offset binary when the OF pin is at a logic low or 2’s complement when the OF pin is at

a logic high. While the sense of this pin may be changed "on the fly," doing this is not recommended as the

output data could be erroneous for a few clock cycles after this change is made.

The INT/EXT REF Pin

The INT/EXT REF pin determines whether the internal reference or an external reference voltage is used. With

this pin at a logic low, the internal 2.0V reference is in use. With this pin at a logic high an external reference

must be applied to the VREF pin, which should then be bypassed to ground. There is no need to bypass the VREF

pin when the internal reference is used. There is no access to the internal reference voltage, but its value is

approximately equal to VRP − VRN. See Reference Pins

DATA OUTPUT PINS

The ADC12D040 has 24 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while

the OE and PD pins are low. While the tOD time provides information about output timing, tOD will change with a

change of clock frequency. At the rated 40 MHz clock rate, the data transition is about 6 to 10 ns after the rise of

the clock and about 4 to 10 ns before the fall of the clock (depending upon VDR), so either clock edge may be

used to capture data, depending upon the data setup time of the circuit accepting the data. Also, circuit board

layout will affect relative delays of the clock and data, so it is important to consider these relative delays when

designing the digital interface. At sample frequencies below 40 MHz, there is a longer time between data

transition and the fall of the clock, so that the falling edge of the clock is generally the best edge to use for output

data capture at low sample rates.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond the specified 20 pF/pin will cause tOD to increase,

making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series resistors of about 100

Ω at the digital

outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the

output currents, which could otherwise result in performance degradation. See Figure 31.

Note that, although the ADC12D040 has Tri-State outputs, these outputs should not be used to drive a bus and

the charging and discharging of large capacitances can degrade SNR performance. Each output pin should drive

only one pin of a receiving device and the interconnecting lines should be as short as practical.

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