ADC12D040

SNAS171E – JUNE 2002 – REVISED MARCH 2013

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If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor at each amplifier output and a capacitor across the analog inputs (as shown

in Figure 32) will improve performance. The LMH6702 and the LMH6628 have been successfully used to drive

the analog inputs of the ADC12D040.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, VREF

should be in the range of

1.0V

≤ VREF ≤ 2.4V

(10)

Operating outside of these limits could lead to performance degradation.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

26

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