-

+

255, 1%

280, 1%

50:

SIGNAL

INPUT

49.9,

1%

68 pF

511, 1%

511, 1%

51

51

68 pF

To ADC

VIN-

To ADC

VIN+

Amplifier:

LMH6650

ADC12D040

www.ti.com

SNAS171E – JUNE 2002 – REVISED MARCH 2013

Figure 32. Differential Drive Circuit using a fully differential amplifier.

Input Common Mode Voltage

The input common mode voltage, VCM, should be of a value such that the peak excursions of the analog signal

does not go more negative than ground or more positive than 1.0 Volts below the VA supply voltage. The nominal

VCM should generally be about VREF/2. VRBA and VRBB can be used as VCM sources as long as no d.c. current is

drawn from these pins.

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, OF, INT/EXT REF, and PD.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 100 kHz to 55 MHz with rise and fall times of less than 3ns. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is what limits the lowest sample

The ADC clock line should be considered to be a transmission line and be series terminated at the source end to

match the source impedance with the characteristic impedance of the clock line. It generally is not necessary to

terminate the far (ADC) end of the clock line, but if a single clock source is driving more than one device (a

condition that is generally not recommended), far end termination may be needed. Far end termination is a series

RC with the resistor being the same as the characteristic impedance of the clock line. The capacitor should have

a minimum value of

(9)

where tPD is the propagation time in ns/unit length, "L" is the length of the line and ZO is the characteristic

impedance of the line. The units of tPD and "L" should be consistent with each other. The typical board of FR-4

material has a tPD of about 150 ps/inch, or about 60 ps/cm.

The far end termination should be near but beyond the ADC clock pin as seen from the clock source.

The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is

specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range of 40% to 60%.

Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application

Note AN-905 (SNLA035) for information on setting characteristic impedance.

OEA, OEB

The OEA and OEB pin, when high, put the output pins of their respective converters into a high impedance state.

When either of these pins is low the corresponding outputs are in the active state. The ADC12D040 will continue

to convert whether these pins are high or low, but the output can not be read while the pin is high.

Copyright © 2002–2013, Texas Instruments Incorporated

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