S25FL256SDPNFVC datasheet(10/149 Pages) CYPRESS

10 / 149 page

Document Number: 001-98283 Rev. *M

Page 9 of 148

S25FL128S/S25FL256S

2.2

Address and Data Configuration

Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data

may be sent back to the host serially on the Serial Output (SO) signal.

Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will be returned to the

host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0 and IO1 or four bit

(nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups

on IO0, IO1, IO2, and IO3.

2.3

RESET#

The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a command. When

RESET# is driven to logic low (VIL) for at least a period of tRP, the device:



terminates any operation in progress,



tristates all outputs,



resets the volatile bits in the Configuration Register,



resets the volatile bits in the Status Registers,



resets the Bank Address Register to zero,



loads the Program Buffer with all ones,



reloads all internal configuration information necessary to bring the device to standby mode,



and resets the internal Control Unit to standby state.

RESET# causes the same initialization process as is performed when power comes up and requires tPU time.

RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a hardware reset should

be reinitiated once the device is ready to accept a command sequence.

When RESET# is first asserted Low, the device draws ICC1 (50 MHz value) during tPU. If RESET# continues to be held at VSS the

device draws CMOS standby current (ISB).

RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.

The RESET# input is not available on all packages options. When not available the RESET# input of the device is tied to the inactive

state, inside the package.

2.4

Serial Clock (SCK)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on

the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands, and after every edge in

DDR commands.

2.5

Chip Select (CS#)

The chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory

device. When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output

signals are high impedance. Unless an internal Program, Erase or Write Registers (WRR) embedded operation is in progress, the

device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power

mode. After Power-up, a falling edge on CS# is required prior to the start of any command.

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