S25FL256SDPNFVC datasheet(6/149 Pages) CYPRESS

6 / 149 page

Document Number: 001-98283 Rev. *M

Page 5 of 148

S25FL128S/S25FL256S

1.2

Migration Notes

1.2.1

Features Comparison

The S25FL128S and S25FL256S devices are command set and footprint compatible with prior generation FL-K and FL-P families.

Notes:

1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.

2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).

3. 64-kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.

4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.

5. Refer to individual data sheets for further details.

Table 1. FL Generations Comparison

Parameter

FL-K

FL-P

FL-S

Technology Node

90 nm

65 nm

Architecture

Floating Gate

MirrorBit

MirrorBit Eclipse

Release Date

In Production

2H2011

Density

4 Mb - 128 Mb

32 Mb - 256 Mb

128 Mb - 256 Mb

Bus Width

x1, x2, x4

Supply Voltage

2.7V - 3.6V

2.7V - 3.6V / 1.65V - 3.6V VIO

Normal Read Speed (SDR)

6 MB/s (50 MHz)

5 MB/s (40 MHz)

6 MB/s (50 MHz)

Fast Read Speed (SDR)

13 MB/s (104 MHz)

17 MB/s (133 MHz)

Dual Read Speed (SDR)

26 MB/s (104 MHz)

20 MB/s (80 MHz)

26 MB/s (104 MHz)

Quad Read Speed (SDR)

52 MB/s (104 MHz)

40 MB/s (80 MHz)

52 MB/s (104 MHz)

Fast Read Speed (DDR)



20 MB/s (80 MHz)

Dual Read Speed (DDR)



40 MB/s (80 MHz)

Quad Read Speed (DDR)



80 MB/s (80 MHz)

Program Buffer Size

256B

256B / 512B

Erase Sector Size

4 kB / 32 kB / 64 kB

64 kB / 256 kB

Parameter Sector Size

4 kB

4 kB (option)

Sector Erase Time (typ.)

30 ms (4 kB), 150 ms (64 kB)

500 ms (64 kB)

130 ms (64 kB), 520 ms (256 kB)

Page Programming Time (typ.)

700 µs (256B)

1500 µs (256B)

250 µs (256B), 340 µs (512B)

OTP

768B (3 x 256B)

506B

1024B

Advanced Sector Protection

Yes

Auto Boot Mode

Yes

Erase Suspend/Resume

Yes

Program Suspend/Resume

Yes

Operating Temperature

40°C to +85°C

40°C to +85°C / +105°C

40°C to +85°C /

+105°C / +125°C

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