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S25FL256SDPNFVC bảng dữ liệu(PDF) 36 Page - Cypress Semiconductor

tên linh kiện S25FL256SDPNFVC
Giải thích chi tiết về linh kiện  128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
PDF  149 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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Document Number: 001-98283 Rev. *M
Page 35 of 148
S25FL128S/S25FL256S
5.5
DDR AC Characteristics
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
5.5.1
DDR Input Timing
Figure 35. SPI DDR Input Timing
Table 14. AC Characteristics — DDR Operation
Symbol
Parameter
66 MHz
80 MHz
Unit
Min
Typ
Max
Min
Typ
Max
FSCK, R
SCK Clock Frequency for DDR READ
instruction
DC
66
DC
80
MHz
PSCK, R
SCK Clock Period for DDR READ
instruction
15
12.5
ns
tWH, tCH Clock High Time
45% PSCK
45% PSCK
ns
tWL, tCL Clock Low Time
45% PSCK
45% PSCK
ns
tCS
CS# High Time (Read Instructions)
10
10
ns
tCSS
CS# Active Setup Time (relative to SCK)
3
3
ns
tCSH
CS# Active Hold Time (relative to SCK)
3
3
ns
tSU
IO in Setup Time
2
3000 (2)
1.5
3000 (2)
ns
tHD
IO in Hold Time
2
1.5
ns
tV
Clock Low to Output Valid
6.5 (1)
6.5 (1)
ns
tHO
Output Hold Time
1.5
1.5
ns
tDIS
Output Disable Time
8
8
ns
tLZ
Clock to Output Low Impedance
0
8
0
8
ns
tO_SKEW First Output to last Output data valid time
600
600
ps
CS#
SCK
SI_or_IO
SO
MSB IN
LSB IN
tCSS
tCSS
tCSH
tCSH
tCS
tSU
tSU
tHD
tHD



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