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S25FL256SDPNFVC bảng dữ liệu(PDF) 87 Page - Cypress Semiconductor

tên linh kiện S25FL256SDPNFVC
Giải thích chi tiết về linh kiện  128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte) 128 Mbit (16 Mbyte)/256 Mbit (32 Mbyte)
PDF  149 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
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S25FL256SDPNFVC bảng dữ liệu(HTML) 87 Page - Cypress Semiconductor

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Document Number: 001-98283 Rev. *M
Page 86 of 148
S25FL128S/S25FL256S
9.4.2
Fast Read (FAST_READ 0Bh or 4FAST_READ 0Ch)
The instruction
0Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
0Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
0Ch is followed by a 4-byte address (A31-A0)
The address is followed by zero or eight dummy cycles depending on the latency code set in the Configuration Register. The dummy
cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data
value on SO is “don’t care” and may be high impedance. Then the memory contents, at the address given, are shifted out on SO.
The maximum operating clock frequency for FAST READ command is 133 MHz.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Figure 9.8 Fast Read (FAST_READ) Command Sequence (3-byte Address, 0Bh [ExtAdd=0, LC=10b])
Figure 9.9 Fast Read Command Sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=10b)
Figure 9.10 Fast Read Command Sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=11b)
1
3
2
10
9
8
7
6
5
4
0
31
30
29
28
Instruction
24-Bit
Address
23
21
22
1
3
2
0
1
3
2
0
7
6
5
4
36
35
34
33
32
39
38
37
1
3
2
0
7
6
5
4
Dummy Byte
44
43
42
41
40
47
46
45
DATA OUT 1
DATA OUT 2
SCK
SI
SO
MSB
High Impedance
7
MSB
CS
#
1
3
2
10
9
8
7
6
5
4
0
39
38
37
36
Instruction
32-Bit
Address
31
29
30
1
3
2
0
1
3
2
0
7
6
5
4
44
43
42
41
40
47
46
45
1
3
2
0
7
6
5
4
Dummy Byte
52
51
50
49
48
55
54
53
DATA OUT 1
DATA OUT 2
SCK
SI
SO
MSB
High Impedance
7
MSB
CS
#
0
1
2
3
4
5
6
7
8
383940414243444546474849
Instruction
32 Bit Address
Data 1
Data 2
7
6
5
4
3
2
1
0
31
1
0
7
6
5
4
3
2
1
0
7
6
CS#
SCK
SI
SO



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