M68HC08 datasheet(92/172 Pages) FREESCALE

92 / 172 page

Timer Interface Module (TIM)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

8.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

8.6.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not

accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait

mode.

If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before

executing the WAIT instruction.

8.6.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect

after an external interrupt.

8.7 TIM During Break Interrupts

A break interrupt stops the TIM counter.

The system integration module (SIM) controls whether status bits in other modules can be cleared during

the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status

bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).)

To allow software to clear status bits during a break interrupt, write a logic one to the BCFE bit. If a status

bit is cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero

(its default state), software can read and write I/O registers during the break state without affecting status

bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on

such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic zero.

After the break, doing the second step clears the status bit.

8.8 I/O Signals

Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1.

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.

PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin.

8.9 I/O Registers

The following I/O registers control and monitor operation of the TIM:

•

TIM status and control register (TSC)

•

TIM counter registers (TCNTH:TCNTL)

•

TIM counter modulo registers (TMODH:TMODL)

•

TIM channel status and control registers (TSC0 and TSC1)

•

TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)

M68HC08 bảng dữ liệu(PDF) 92 Page - Freescale Semiconductor, Inc

M68HC08 bảng dữ liệu(HTML) 92 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL