M68HC08 datasheet(28/172 Pages) FREESCALE

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Memory

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

2.6 Functional Description

The FLASH memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user

vectors. The minimum size of FLASH memory that can be erased is 64 bytes (a page); and the maximum

size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and

erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these

operations appear later in this section. The address ranges for the user memory and vectors are:

•

$EC00–$FBFF; user memory; 4,096 bytes; MC68H(R)C908JL3E/JK3E

$F600–$FBFF; user memory; 1,536 bytes;

MC68H(R)C908JK1E

•

$FFD0–$FFFF; user interrupt vectors; 48 bytes

NOTE

An erased bit reads as logic 1 and a programmed bit reads as logic 0.

A security feature prevents viewing of the FLASH contents.(1)

2.7 FLASH Control Register

The FLASH Control Register controls FLASH program and erase operations.

HVEN — High Voltage Enable Bit

This read/write bit enables high voltage from the charge pump to the memory for either program or

erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program

or erase is followed.

1 = High voltage enabled to array and charge pump on

0 = High voltage disabled to array and charge pump off

MASS — Mass Erase Control Bit

This read/write bit configures the memory for mass erase operation or page erase operation when the

ERASE bit is set.

1 = Mass erase operation selected

0 = Page erase operation selected

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be

set to 1 at the same time.

1 = Erase operation selected

0 = Erase operation not selected

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for

unauthorized users.

Address:

$FE08

Bit 7

654321

Bit 0

Read:

0000

HVEN

MASS

ERASE

PGM

Write:

Reset:

00000000

Figure 2-4. FLASH Control Register (FLCR)

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