M68HC08 datasheet(62/172 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

Figure 5-11

. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the

INT1 RTI prefetch, this is a redundant operation.

NOTE

To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifies the H register or uses the indexed addressing mode, software

should save the H register and then restore it prior to exiting the routine.

5.5.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the

interrupt mask (I bit) in the condition code register.

NOTE

A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware interrupt does.

5.5.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the

interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be

useful for debugging.

CLI

LDA

INT1

PULH

RTI

INT2

BACKGROUND ROUTINE

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

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