M68HC08 datasheet(55/172 Pages) FREESCALE

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SIM Bus Clock Control and Generation

MC68HC908JL3E Family Data Sheet, Rev. 3

Freescale Semiconductor

5.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The

system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.

Figure 5-3. SIM Clock Signals

5.2.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (2OSCOUT) divided by four.

5.2.2 Clock Start-Up from POR

When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive

and held in an inactive phase until after the 4096 2OSCOUT cycle POR time-out has completed. The RST

pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the

time-out.

5.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM

counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This

time-out is selectable as 4096 or 32 2OSCOUT cycles. (See 5.6.2 Stop Mode.)

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.

Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.

Some modules can be programmed to be active in wait mode.

$FE04

Interrupt Status Register 1

(INT1)

Read:

IF5

IF4

IF3

IF1

Write:

RRRRRRRR

Reset:

00000000

$FE05

Interrupt Status Register 2

(INT2)

Read:

IF14

0000000

Write:

RRRRRRRR

Reset:

00000000

$FE06

Interrupt Status Register 3

(INT3)

Read:

0000000

IF15

Write:

RRRRRRRR

Reset:

00000000

= Unimplemented

= Reserved

Figure 5-2. SIM I/O Register Summary

÷ 2

BUS CLOCK

GENERATORS

SIM

SIM COUNTER

From

OSCILLATOR

From

OSCILLATOR

OSCOUT

2OSCOUT

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