TMP93CS41 datasheet(208/248 Pages) TOSHIBA

208 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-206

WDMOD

Bit symbol

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

(005CH)

Read/Write

R/W

After reset

Function

WDT

control

1: Enable

Select detection time

00: 2

15/fSYS

01: 2

17/fSYS

10: 2

19/fSYS

11: 2

21/fSYS

See Figure 3.13.6

Warm-up

time

Standby mode

00: RUN mode

01: STOP mode

10: IDLE1 mode

11: IDLE2 mode

1: Internally

connects

WDT out

to the

reset pin

1: Drives

the pin

even in

STOP

mode

Figure 3.13.4 Watchdog Timer Mode Register

−

Connects WDT out to reset

Watchdog timer out control

Selection of warm-up time

Warm-up Time

T45CR<QCU> = 0

T45CR<QCU> = 1

System Clock

Selection

<SYSCK>

Gear Value

<GEAR2:0>

WARM

= 0WARM = 1

WARM

= X

1 (fs)

XXX

(Don’t care)

0.50 s

2.00 s

3.9 ms

000 (fc)

0.82 ms

3.28 ms

6.4

µs

001 (fc/2)

1.64 ms

6.55 ms

12.8

µs

010 (fc/4)

3.28 ms

13.11 ms

25.6

µs

011 (fc/8)

6.55 ms

26.21 ms

51.2

µs

0 (fc)

100 (fc/16)

13.11 ms

52.43 ms

102.4

µs

Disable

Enable

Watchdog timer enable/disable control

DRVE (Explanation in STOP mode section)

RUN mode (only the CPU stops)

STOP mode (All circuits stop)

IDLE1 mode (only the oscillator operates)

IDLE2 mode (CPU and AD stop)

Select the standby mode HALT instruction

at fc

= 20 MHz, fs = 32.768 kHz

TMP93CS41 bảng dữ liệu(PDF) 208 Page - Toshiba Semiconductor

TMP93CS41 bảng dữ liệu(HTML) 208 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL