TMP93CS41 datasheet(206/248 Pages) TOSHIBA

206 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-204

The watchdog timer consists of 7-stage and 15-stage binary counters which use the

system clock (fSYS) as the input clock. The 15-stage binary counter has fSYS/215, fSYS/217,

fSYS/219 and fSYS/221 outputs. Selecting one of the outputs with the WDMOD<WDTP1:0>

occurs.

For the warm-up counter, either a 27 or a 29 output from the 15-stage binary counter can

be selected using the WDMOD<WARM> register. When a stable-external oscillator is used,

a shorter warm-up time is available using the T45CR<QCU> register. When <QCU>

= “1”,

a counting value 27 is selected.

When the watchdog timer is in operation, this shorter warm-up time function cannot be

selected. The warm-up counter function can be made available by setting <QCU>

= “0”.

Since the watchdog timer out pin ( WDTOUT ) outputs “0” when there is a watchdog timer

overflow, the peripheral devices can be reset. The watchdog timer out pin is set to “1” after

WDT has been disabled and the watchdog timer cleared (by a clear code 4EH being written

into the WDCR register).

Example:

LDW (WDMOD), B100H

; Disable

(WDCR), 4EH

; Write clear code

SET

7, (WDMOD)

; Enable again

In other words, WDTOUT keeps outputting “0” until the clear code is written.

The watchdog timer out pin can also be connected to the reset pin internally. In this case,

the watchdog timer out pin ( WDTOUT ) outputs “0” for 8 to 20 states (12.8 to 32

µs at fc = 20

MHz), and then resets itself.

Figure 3.13.2 Normal Mode

Figure 3.13.3 Reset Mode

Write clear code

WDT counter

WDT interrupt

WDT clear

(Software)

WDTOUT

Overflow

8 to 20 states

= 12.8 to 32 µs (at 20 MHz)

WDT counter

WDT interrupt

WDTOUT

(Internal reset)

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