TMP93CS41 datasheet(28/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-26

Table 3.3.5 I/O Operation during HALT Mode

HALT mode

RUN

IDLE2

IDLE1

STOP

WDMOD<HALTM1:0>

CPU

HALT

I/O port

Maintain the state when the HALT instruction was executed.

See Table 3.3.8

8-bit timer

8-bit PWM timer

16-bit timer

Pattern generator

Serial interface

AD converter

Watchdog timer

Interrupt controller

(2) How to release the HALT mode

These halt states can be released by resetting or by requesting an interrupt. The halt

release sources are determined by the combinations between the states of the interrupt

mask register<IFF2:0> and the HALT modes. The details for releasing the halt status

are shown in Table 3.3.6.

•

Release by requesting an interrupt

This method of releasing operation from the HALT mode depends on the

interrupt-enabled status being in force. When the interrupt request level set before

executing the HALT instruction exceeds the value of the interrupt mask register,

the interrupt due to that source is processed after releasing the HALT mode, and

then the CPU starts executing the next instruction that follows the HALT

instruction. When the interrupt request level set before executing the HALT

instruction is less than the value of the interrupt mask register, release of the

HALT mode is not executed. (In non-maskable interrupts, interrupt processing is

preformed after releasing the HALT mode regardless of the value of the mask

INT0 interrupts are a special case in which release of the HALT mode is

executed even if the interrupt request level set before executing the HALT

instruction is less than the value of the interrupt mask register. In this case

interrupt processing is not performed, and the CPU starts executing the next

instruction that follows the HALT instruction, but the interrupt request flag is

held at 1.

Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,

INT0) which can release the HALT mode may not be able to do so if they are

input during the period CPU is shifting to the HALT mode (for about 3 clocks of

fFPH) with IDLE1 or STOP mode (IDLE2 and RUN are not applicable to this

case). (In this case, an interrupt request is kept on hold internally.)

If another interrupt is generated after it has shifted to HALT mode completely,

halt status can be released without difficultly. The priority of this interrupt is

compare with that of the interrupt kept on hold internally, and the interrupt with

higher priority is handled first followed by the other interrupt.

•

Release by resetting

Resetting releases all halt status settings.

It is necessary to allow enough resetting time (3 ms or more) for the operation of

the oscillator to stabilize.

Operate

STOP

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