TMP93CS41 datasheet(52/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-50

(2) External interrupt control

Interrupt Input Mode Control Register

IIMC

Bit symbol

I0IE

I0LE

NMIREE

(007BH)

Read/Write

After reset

Function

1: INT0

input

enable

0: INT0

edge-

sense

mode

1: INT0

level-

sense

mode

1: Can be

accepted

in NMI

rising

edge.

Figure 3.4.6 Interrupt Input Mode Control Register

Table 3.4.2 Setting of External Interrupt Pin Function

Interrupt

Pin Name

Mode

Setting Method

Falling edge

IIMC<NMIREE>

= 0

NMI

−

Falling and rising

edges

IIMC<NMIREE>

= 1

Rising edge

IIMC<I0LE>

= 0, <I0lE> = 1

INT0

P87

High level

IIMC<I0LE>

= 1, <I0lE> = 1

Rising edge

T4MOD<CAP12M1:0>

= 0, 0 or 0, 1 or 1, 1

INT4

P80

Falling edge

T4MOD<CAP12M1:0>

= 1, 0

INT5

P81

Rising edge

T5MOD<CAP34M1:0>

= 0, 0 or 0, 1 or 1, 1

INT6

P84

Falling edge

T5MOD<CAP34M1:0>

= 1, 0

INT7

P85

Rising edge

Note 1: The INT0 pin can also be used for standby release as described in section 3.3.4. Even

if the pin is not used for standby release, setting this register to “0” maintains the port

function during standby mode.

Note 2: This is a case of changing from level-sence to edge-sence for INT0 pin mode.

Execution example:

LD (INTE0AD)

,xxxx0000B

; INT0 disable, clear the request flag.

LD (IIMC)

,xxxxx10xB

; Change from level to edge.

LD (INTE0AD)

,xxxx0nnnB

; Set interrupt level “n” for INT0, clear

the request flag.

Note 3: Read-modify-write is prohibited.

Note 4: IMC<bit7:3> are always read as “1”.

Note 5: See electrical characteristics in section 4 for external interrupt input pulse.

INT0 input enable (Note 1)

INT0 disable (P87 function only)

Input enable

NMI

rising edge enable

Interrupt request generation at

falling edge

Interrupt request generation at

rising and falling edge

INT0 level enable (Note 2)

Rising edge detect interrupt

High level interrupt

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