TMP93CS41 datasheet(195/248 Pages) TOSHIBA

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TMP93CS40/TMP93CS41

2004-02-10

93CS40-193

Protocol

1. Select 9-bit UART mode for the master and slave controllers.

2. Set the SC0MOD<WU> bit of each slave controller to 1 to enable data receiving.

3. The master controller transmits one-frame data including the 8-bit select code for the

slave controllers. The MSB (bit8)<TB8> is set to “1”.

4. Each slave controller receives the above frame and clears its WU bit to “0” if the above

select code matches its own select code.

5. The master controller transmits data to the specified slave controller (the one whose

SC0MOD<WU> bit is cleared to “0”). The MSB (bit8)<TB8> is cleared to “0”.

6. The other slave controllers (those with their <WU> bits remaining at 1) ignore the

receiving data because their MSBs (bit8 or <RB8>) are set to “0” to disable the INTRX0

interrupt.

Slave controllers (with WU

= 0) can transmit data to the master controller. In this way

they can indicate the end of data reception to the master controller.

Bit0

Start

Select code of slave controller

Stop

“1”

Bit8

Bit0

Start

Data

Stop

“0”

TMP93CS41 bảng dữ liệu(PDF) 195 Page - Toshiba Semiconductor