TMP93CS41 datasheet(192/248 Pages) TOSHIBA

192 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-190

2. Receiving

In SCLK output mode, the synchronous clock is output from the SCLK0 pin and data

are shifted into the receiving buffer 1 whenever the receive interrupt flag

INTES0<IRX0C> is cleared by a read of the received data. When 8-bit data is received,

the data will be transferred to receiving buffer 2 (SC0BUF) according to the timing

shown below and INTES0<IRX0C> will be set again, generating an INTRX0 interrupt.

Figure 3.11.22 Receiving Operation in I/O Interface Mode (SCLK0 output mode)

(Channel 0)

In SCLK input mode, the data are shifted to receiving buffer 1 when the SCLK input

becomes active after the receive interrupt flag INTES0<IRX0C> is cleared by a read of

the received data. When 8-bit data are received, the data will be shifted to receiving

buffer 2 (SC0BUF) according to the timing shown below and INTES0<IRX0C> will be

set again, generating the INTRX0 interrupt.

Figure 3.11.23 Receiving Operation in I/O Interface Mode (SCLK input mode) (Channel 0)

Note:

When receiving data, the system must be put in receive enable state

(SC0MOD<RXE> = 1).

SCLK0 input

(SCLKS

= 0: Rising edge mode)

Bit0

RXD0

Timing to shift data

into receiving

buffer 2

Bit1

Bit6

Bit7

Bit2

Generate

INTRX0

SCLK0 input

(SCLKS

= 1: Falling edge mode)

Bit0

RXD0

Bit1

Bit7

IRX0C

SCLK0

Timing to shift data

into receiving buffer 2

Bit2

Generate

INTRX0

Bit6

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