TMP93CS41 datasheet(145/248 Pages) TOSHIBA

145 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-143

The TREG4 timer register is a double buffer structure, which is paired with a register

buffer. The timer control register T45CR<DB4EN> controls whether the double buffer

structure should be enabled or disabled. It is disabled when <DB4EN>

= 0, and enabled

when <DB4EN>

= 1.

When the double buffer is enabled, the timing of data transfer from the register buffer to

the timer register is at the match between the up counter (UC4) and timer register TREG5.

When reset, <DB4EN> will be initialized to “0”; this disables the double buffer. To use the

double buffer, write data in the timer register, set <DB4EN>

= 1, and then write the data

which follows to the register buffer.

TREG4 and the register buffer are allocated to the same memory addresses

000030H/000031H. When <DB4EN>

= 0, the same value will be written in both the timer

= 1, the value is written only into the

buffer should be disabled.

4. Capture registers

These 16-bit registers are used to hold the values of the up counter.

Data in the capture registers should be read all 16 bits. For example, by a 2-byte data

load instruction or by two 1-byte data load instructions, starting from the lower 8 bits

followed by the upper 8 bits.

Lower 8 bits

(TREG4L)

Upper 8 bits

(TREG4H)

TREG5

000033H

000032H

000041H

000040H

TREG6

000031H

000030H

TREG4

Lower 8 bits

(TREG6L)

Upper 8 bits

(TREG6H)

Lower 8 bits

(TREG5L)

Upper 8 bits

(TREG5H)

TREG7

000043H

000042H

Lower 8 bits

(TREG7L)

Upper 8 bits

(TREG7H)

Timer 4

Timer 5

Lower 8 bits

(CAP1L)

Upper 8 bits

(CAP1H)

CAP2

000037H

000036H

000045H

000044H

CAP3

000035H

000034H

CAP1

Lower 8 bits

(CAP3L)

Upper 8 bits

(CAP3H)

Lower 8 bits

(CAP2L)

Upper 8 bits

(CAP2H)

CAP4

000047H

000046H

Lower 8 bits

(CAP4L)

Upper 8 bits

(CAP4H)

Timer 4

Timer 5

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