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TMP93CS41 bảng dữ liệu(PDF) 141 Page - Toshiba Semiconductor |
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TMP93CS41 bảng dữ liệu(HTML) 141 Page - Toshiba Semiconductor |
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141 / 248 page ![]() TMP93CS40/TMP93CS41 2004-02-10 93CS40-139 7 6 5 4 3 2 1 0 Bit symbol QCU PG1T PG0T DB6EN DB4EN Read/Write R/W R/W After reset 0 0 0 0 0 Double buffer 0: Disable 1: Enable Function Warm-up timer control PG1 shift trigger 0: 8-bit timer trigger (Timers 0, 1) 1: 16-bit timer trigger (Timer 5) PG0 shift trigger 0: 8-bit timer trigger (Timers 0, 1) 1: 16-bit timer trigger (Timer 4) Double buffer of TREG6 Double buffer of TREG4 Note 1: In case of not using the 7 stage binary counter as a warm-up timer, a stable clock signal must be input from an external circuit. Note 2: T45CR<bit6:4> are always read as “1”. Figure 3.9.9 16-Bit Timer Trigger Control Register (T45CR) 0 8-bit timer trigger (Timers 0 and 1) 1 16-bit timer trigger (Timer 4) Selecting PG0 shift trigger 0 Disable 1 Enable Double buffer control 0 8-bit timer trigger (Timers 0 and 1) 1 16-bit timer trigger (Timer 5) Selecting PG1 shift trigger 0 Uses 7 stage binary counter 1 Does not use 7 stage binary counter (Note 1) Warm-up timer input control DB6EN: Double buffer of TREG6 DB4EN: Double buffer of TREG4 T45CR (003AH) |
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