TMPR4937 datasheet(312/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-54

10.4.27 PCI Bus Arbiter Broken Master Register (PBABM)

0xD110

This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to

the PCI Master device that was acknowledged as the Broken Master when the Broken Master Check

Enable bit (BMCEN) in the PCI Bus Arbiter Configuration Register (PBACFG) is set.

Regardless of the value of the Broken Master Check Enable bit, a PCI Master device is removed from

the arbitration scheme when “1” is written to the corresponding BM bit.

This register must be cleared to “0” since bit mapping changes, making this register value invalid

when the PCI Bus Arbiter Request Port Register (PBAREQPORT) is changed.

This register is only valid when using the on-chip PCI Bus Arbiter.

Reserved

: Type

: Initial value

Reserved

BM_A BM_B BM_C BM_D BM_W BM_X BM_Y BM_Z

R/W

: Type

0x00

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:8

Reserved

⎯

BM_A

Broken Master

Broken Master A (Default: 0)

Indicates whether PCI Bus Master A is a Broken Master.

1: PCI Bus Master A was acknowledged as a Broken Master.

0: PCI Bus Master A was not acknowledged as a Broken Master.

R/W

BM_B

Broken Master

Broken Master B (Default: 0)

Indicates whether PCI Bus Master B is a Broken Master.

1: PCI Bus Master B was acknowledged as a Broken Master.

0: PCI Bus Master B was not acknowledged as a Broken Master.

R/W

BM_C

Broken Master

Broken Master C (Default: 0)

Indicates whether PCI Bus Master C is a Broken Master.

1: PCI Bus Master C was acknowledged as a Broken Master.

0: PCI Bus Master C was not acknowledged as a Broken Master.

R/W

BM_D

Broken Master

Broken Master D (Default: 0)

Indicates whether PCI Bus Master D is a Broken Master.

1: PCI Bus Master D was acknowledged as a Broken Master.

0: PCI Bus Master D was not acknowledged as a Broken Master.

R/W

BM_W

Broken Master

Broken Master W (Default: 0)

Indicates whether PCI Bus Master W is a Broken Master.

1: PCI Bus Master W was acknowledged as a Broken Master.

0: PCI Bus Master W was not acknowledged as a Broken Master.

R/W

BM_X

Broken Master

Broken Master X (Default: 0)

Indicates whether PCI Bus Master X is a Broken Master.

1: PCI Bus Master X was acknowledged as a Broken Master.

0: PCI Bus Master X was not acknowledged as a Broken Master.

R/W

BM_Y

Broken Master

Broken Master Y (Default: 0)

Indicates whether PCI Bus Master Y is a Broken Master.

1: PCI Bus Master Y was acknowledged as a Broken Master.

0: PCI Bus Master Y was not acknowledged as a Broken Master.

R/W

BM_Z

Broken Master

Broken Master Z (Default: 0)

Indicates whether PCI Bus Master Z is a Broken Master.

1: PCI Bus Master Z was acknowledged as a Broken Master.

0: PCI Bus Master Z was not acknowledged as a Broken Master.

R/W

Figure 10.4.25 PCI Bus Arbiter Broken Master Register

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