TMPR4937 datasheet(308/552 Pages) TOSHIBA

308 / 552 page

Chapter 10 PCI Controller

10-50

Bit

Mnemonic

Field Name

Description

Read/Write

Reserved

⎯

18:16

ReqDP

Request D Port

Request D Port (Default: 100)

Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter

Request D Port (Master D).

111: Makes the PCI Controller Master D.

110: Reserved

101: Reserved

100: Reserved

011: Makes REQ*[3] Master D.

010: Makes REQ*[2] Master D.

001: Makes REQ*[1] Master D.

000: Makes REQ*[0] Master D.

R/W

Reserved

⎯

14:12

ReqWP

Request W Port

Request W Port (Default: 011)

Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter

Request W Port (Master W).

111: Makes the PCI Controller Master W.

110: Reserved

101: Reserved

100: Reserved

011: Makes REQ*[3] Master W.

010: Makes REQ*[2] Master W.

001: Makes REQ*[1] Master W.

000: Makes REQ*[0] Master W.

R/W

Reserved

⎯

10:8

ReqXP

Request X Port

Request X Port (Default: 010)

Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter

Request X Port (Port X).

111: Makes the PCI Controller Master X.

110: Reserved

101: Reserved

100: Reserved

011: Makes REQ*[3] Master X.

010: Makes REQ*[2] Master X.

001: Makes REQ*[1] Master X.

000: Makes REQ*[0] Master X.

R/W

Reserved

⎯

6:4

ReqYP

Request Y Port

Request Y Port (Default: 001)

Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter

Request Y Port (Port Y).

111: Makes the PCI Controller Master Y.

110: Reserved

101: Reserved

100: Reserved

011: Makes REQ*[3] Master Y.

010: Makes REQ*[2] Master Y.

001: Makes REQ*[1] Master Y.

000: Makes REQ*[0] Master Y.

R/W

Reserved

⎯

2:0

ReqZP

Request Z Port

Request Z Port (Default: 000)

Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter

Request Z Port (Port Z).

111: Makes the PCI Controller Master Z.

110: Reserved

101: Reserved

100: Reserved

011: Makes REQ*[3] Master Z.

010: Makes REQ*[2] Master Z.

001: Makes REQ*[1] Master Z.

000: Makes REQ*[0] Master Z.

R/W

Figure 10.4.21 PCI Bus Arbiter Request Port Register (2/2)

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