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TMPR4937 bảng dữ liệu(PDF) 236 Page - Toshiba Semiconductor

tên linh kiện TMPR4937
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 bảng dữ liệu(HTML) 236 Page - Toshiba Semiconductor

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Chapter 9 SDRAM Controller
9-20
9.4.2
SDRAM Timing Register (SDCTR)
0x8040
63
48
Reserved
:Type
:Initial value
47
34
33
32
Reserved
DIA
R/W
:Type
1
1
:Initial value
31
29
28
27
26
25
24
23
22
18
17
16
BC
ACP
PT
RCD
ACE
PDAE
RC
CASL
DRB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W :Type
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
:Initial value
15
14
13
12
11
0
DA
SWB
Reserved
RP
R/W
R/W
R/W
:Type
1
1
0x30C
:Initial value
Bit
Mnemonic
Field Name
Description
Read/Write
63:34
—
—
Reserved
⎯
33:32
DIA
Write Active
Period
Data In to Active(tDAL) (Default: 11)
Specifies the period from the last Write data to the Active command.
00: Reserved
01: 4 tCK
1
10: 5 tCK
11: 6 tCK
R/W
31:29
BC
Bank Cycle Time
Bank Cycle Time (tRC) (Default: 101)
Specifies the bank cycle time.
2
000: 5 tCK 100: 9 tCK
001: 6 tCK 101: 10 tCK
010: 7 tCK 110: Reserved
011: 8 tCK 111: Reserved
R/W
28:27
ACP
Active Command
Time
Active Command Period (tRAS) (Default: 11)
Specifies the active command time.
00: 3 tCK
01: 4 tCK
10: 5 tCK
11: 6 tCK
R/W
26
PT
Precharge Time
Precharge Time (tRP) (Default: 1)
Specifies the precharge time.
0: 2 tCK
1: 3 tCK
R/W
25
RCD
RAS-CAS Delay
RAS to CAS Delay (tRCD) (Default: 1)
Specifies the RAS - CAS delay.
0: 2 tCK
1: 3 tCK
R/W
Figure 9.4.2 SDRAM Timing Register (1/2)
1 tCK = Clock cycle
2 tRC is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is tRAS +
tRP + 1tCK if tRAS + tRP < tRC in the case of (ii) (iii).



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