TMPR4937 datasheet(235/552 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-19

Bit

Mnemonic

Field Name

Description

Read/Write

Registered DIMM Registered DIMM (Default: 0)

Specifies whether the SDRAM connected to the channel is Registered

memory.

0: Disable Registered memory

1: Enable Registered memory

R/W

14:13

—

Reserved

⎯

Master Enable

Master Enable (Default: 0)

Specifies during ECC initialization whether a channel will be made the

Master channel.

0: Disable

1: Enable

R/W

Slave Enable

Slave Enable (Default: 0)

Specifies during ECC initialization whether a channel will be made the

Slave channel.

0: Disable

1: Enable

R/W

Channel Enable

Enable (Default: 0)

Specifies whether to enable a channel.

0: Disable1: Enable

R/W

—

Reserved

⎯

Bank Count

Number of Banks (Default: 0)

Specifies the bank count.

0: 2 banks

1: 4 banks

R/W

—

Reserved

⎯

6:5

Row Size

Row Size (Default: 00)

Specifies the row size.

00: 2048 Rows (11 bits)

01: 4096 Rows (12 bits)

10: 8192 Rows (13 bits)

11: Reserved

R/W

4:2

Column Size

Column Size (Default: 000)

Specifies the column size.

000: 256 words (8 bits)

001: 512 words (9 bits)

010: 1024 words (10 bits)

011: 2048 words (11 bits)

100: 4096 words (12 bits)

101-111: Reserved

R/W

—

Reserved

⎯

Memory Width

Memory Width (Default: 0)

Specifies the bus width.

0: 64 bits 1: 32 bits

R/W

Figure 9.4.1 SDRAM Channel Control Register (2/2)

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