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TMPR4937 bảng dữ liệu(PDF) 192 Page - Toshiba Semiconductor

tên linh kiện TMPR4937
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4937 bảng dữ liệu(HTML) 192 Page - Toshiba Semiconductor

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Chapter 8 DMA Controller
8-36
8.4.7
DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)
Offset Address: DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3)
DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3)
63
48
Reserved
: Type
: Initial value
47
32
Reserved
: Type
: Initial value
31
24
23
16
Reserved
SADINC[23:16]
R/W
: Type
⎯
: Initial value
15
0
SADINC[15:0]
R/W
: Type
⎯
: Initial value
Bit
Mnemonic
Field Name
Description
Read/Write
63:24
Reserved
⎯
23:0
SADINC
Source Address
Increment
Source Address Increment (Default: undefined)
This field sets the increase/decrease value of the DMA Source Address
Register (DMSARn). This value is a 24-bit two’s complement and indicates
a byte count.
Refer to “8.3.7.1 Channel Register Settings During Single Address
Transfer” and “8.3.8.1 Channel Register Settings During Dual Address
Transfer” for more information.
R/W
Figure 8.4.7 DMA Source Address Increment Register



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