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TMPR4937 bảng dữ liệu(PDF) 185 Page - Toshiba Semiconductor |
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TMPR4937 bảng dữ liệu(HTML) 185 Page - Toshiba Semiconductor |
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185 / 552 page  Chapter 8 DMA Controller 8-29 Bit Mnemonic Field Name Description Read/Write 16 EXTRQ External Request External Request (Default: 0) Sets the Request Transfer mode. 1: I/O DMA transfer mode This bit is used by the External I/O DMA Transfer mode and the Internal I/O DMA Transfer mode. A channel requests internal bus ownership when the I/O device asserts the DMA request signal. 0: Memory Transfer mode This bit is used by the Memory-Memory Copy Transfer mode and the Memory Fill Transfer mode. A channel requests internal bus ownership when the value of DMCSRn.WAITC becomes “0”. R/W 15:13 STLTIME / INTRQD Transfer Stall Detection Interval/Internal Request Delay • When in the I/O DMA Transfer mode (DMCCRn.EXTRQ is “1”) Stalled Transfer Detect Time (Default: 000) Sets the detection interval for a lack of bus ownership. If this channel n releases bus ownership then the interval it does not have ownership exceeds the clock count set by this field, then DMCSRn.STLXFER is set to “1”. Refer to “0 Transfer Stall Detection Function” for more information. 000: Does not detect stalled transfers. 001: Sets 960 (15 × 64) clocks as the detection interval 010: Sets 4032 (63 × 64) clocks as the detection interval 011: Sets 16320 (255 × 64) clocks as the detection interval 100: Sets 65472 (1023 × 64) clocks as the detection interval 101: Sets 262080 (4095 × 64) clocks as the detection interval 110: Sets 1048512 (16383 × 64) clocks as the detection interval 111: Sets 4194240 (65535 × 64) clocks as the detection interval • When in the Memory Transfer mode (DMCCRn.EXTRQ is “0”) Internal Request Delay (Default: 000) Sets the delay time from when bus ownership is released to the next bus ownership request. Bus ownership is released, the set delay time elapses, then a bus ownership request is generated from the channel. 000: Always requests bus ownership when this channel is active. (Bus ownership is released after bus operation ends) 001: Set 16 clocks as the delay time 010: Set 32 clocks as the delay time 011: Set 64 clocks as the delay time 100: Set 128 clocks as the delay time 101: Set 256 clocks as the delay time 110: Set 512 clocks as the delay time 111: Set 1024 clocks as the delay time R/W 12 INTENE Error Interrupt Enable Interrupt Enable on Error (Default: 0) Enables interrupts when the Error End bit (DMCSRn.ABCHC) or the Transfer Stall Detection bit (DMCSRn.STLXFER) is set. 1: Generates interrupts. 0: Does not generate interrupts. R/W 11 INTENC Chain End Interrupt Enable Interrupt Enable on Chain Done (Default: 0) This bit enables interrupts when the Chain End bit (DMCSRn.NCHNC) is set. 1: Generate interrupts. 0: Do not generate interrupts. R/W 10 INTENT Transfer End Interrupt Enable Interrupt Enable on Transfer Done (Default: 0) This bit enables interrupts when the Transfer End bit (DMCSRn.NTRNFC) is set. 1: Generate interrupts. 0: Do not generate interrupts. R/W Figure 8.4.2 DMA Channel Control Register (3/4) |
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