TMPR4937 datasheet(178/552 Pages) TOSHIBA

178 / 552 page

Chapter 8 DMA Controller

8-22

8.3.14 Arbitration Among DMA Channels

The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four

DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the

round robin method and the fixed priority method. (See Figure 8.3.7.) The Round Robin Priority bit

(RRPT) of the DMA Master Control Register (DMMCR) selects the priority method.

•

Fixed priority (DMMCR.RRPT

= 0)

As shown below, Channel 0 has the highest priority and Channel 3 has the lowest priority.

CH0 > CH1 > CH2 > CH3

•

Round Robin method (DMMCR.RRPT

= 1)

The last channel to perform DMA transfer has the lowest priority.

•

After CH0 DMA transfer execution: CH1 > CH2 > CH3 > CH0

•

After CH1 DMA transfer execution: CH2 > CH3 > CH0 > CH1

•

After CH2 DMA transfer execution: CH3 > CH0 > CH1 > CH2

•

After CH3 DMA transfer execution: CH0 > CH1 > CH2 > CH3

a) Fixed Priority is selected

b) Round Robin Priority is selected

Figure 8.3.7 DMA Channel Arbitration

8.3.15 Restrictions in Access to PCI Bus

The PCI Controller detects a bus error if the DMA Controller performs one of the following accesses

to the PCI Bus.

•

Burst transfer exceeding 8 double words (PCICSTATUS.TLB)

•

Address Increment value –8 Burst transfer (PCICSTATUS.NIB)

•

Address Increment Value 0 Burst transfer (PCICSTATUS.ZIB)

•

Dual Address Burst transfer when the setting for DMSARn, DMDARn, or DMCNTRn is not a

double word boundary (PCICSTATUS.IAA)

In addition, Single Address transfers between an external I/O device and the PCI Bus are not

supported. Data transfer is not performed, but no error is detected.

Channel 0

Channel 1

Channel 2

Channel 3

Channel 0

Channel 2

Channel 1

Channel 3

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