TMPR4937 datasheet(427/552 Pages) TOSHIBA

427 / 552 page

Chapter 14 AC-link Controller

14-21

Bit

Mnemonic Field Name

Description

Read/Write

Reserved

⎯

AUDIDMA: Disable Audio Receive-data DMA.

W1C

—

W1C

0: No effect

1: Disables audio receive-data DMA.

LFEDMA: Disable Audio LFE Transmit-data DMA.

W1C

—

W1C

0: No effect

1: Disables audio LFE transmit-data DMA.

CENTDMA: Disable Audio Center Transmit-data DMA.

W1C

—

W1C

0: No effect

1: Disables audio Center transmit-data DMA.

SURRDMA: Disable Audio Surround L&R Transmit-data DMA.

W1C

—

W1C

0: No effect

1: Disables audio Surround L&R transmit-data DMA.

AUDODMA: Disable Audio PCM L&R Transmit-data DMA.

W1C

—

W1C

0: No effect

1: Disables audio PCM L&R transmit-data DMA.

7:5

Reserved

⎯

MICSEL: MIC Selection

W1C

—

W1C

0: No effect

1: Selects PCM L&R (Slot 3&4) for audio reception

WRESET: Deassert Warm Reset.

W1C

—

W1C

0: No effect

1: Deasserts warm reset.

[Note: The software must guarantee the warm reset assertion

time meets the AC’97 specification (1.0

µs or more).]

WAKEUP: Disable Wake-up.

W1C

—

W1C

0: No effect

1: Disables wake-up from low-power mode.

LOWPWR: Disable AC-link Low-power Mode.

W1C

—

W1C

0: No effect

1: Releases SYNC and SDOUT signals from low.

ENLINK: Disable AC-link.

W1C

—

W1C

0: No effect

1: Asserts the ACRESET* signal to AC-link.

[Note: The software must guarantee the ACRESET* signal

assertion time meets the AC’97 specification (1.0

µs or

more).]

Figure 14.4.2 ACCTLDIS Register (2/2)

Clear xxxxDMA bits in ACCTLEN to “0” by using this register to disable transmit/receive-data

DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while

output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This

behavior will not occur if the software waits for data-flow completion by detecting underrun before it

disables the corresponding slot.

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