TMPR4937 datasheet(367/552 Pages) TOSHIBA

367 / 552 page

Chapter 11 Serial I/O Port

11-7

11.3.4 Data Reception

When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set

to “0”, reception operation starts after the RXD signal start bit is detected. Start bits are detected when

the RXD signal transitions from the High state to the Low state. Therefore, the RXD signal is not

interpreted as a start bit if it is Low when the Serial Data Reception Disable bit is set to “0”.

The received data are stored in the Receive FIFO. The Reception Data Full bit (RDIS) of the

DMA/Interrupt Status Register (SIDISRn) is set if the byte count of the stored reception data exceeds

the value set by the Receive FIFO Request Trigger Level field (RDIL) of the FIFO Control Register

(SIFCRn).

An interrupt is signaled when the Reception Data Interrupt Enable bit (RIE) of the DMA/Interrupt

Control Register (SIDICRn) is set. The received data can be read from the Receive FIFO Data Register

(SIRFIFOn).

In addition, DMA transfer is initiated when the Reception Data DMA Enable bit (RDE) of the

DMA/Interrupt Control Register (SIDICRn) is set.

11.3.5 Data Transmission

Data stored in the Transmission Data FIFO are transmitted when the Serial Data Transmission

Disable bit (TSDE) of the Flow Control Register (SIFLCRn) is set to “0”.

If the available space in the Transmit FIFO is equal to or greater than the byte count set by the

Transmit FIFO Request Trigger Level (TDIL) of the Control Register (SIFCRn), the transmission data

empty bit (TDIS) of the DMA/Interrupt Status Register (SIDISRn) is set.

An interrupt is signaled when the Transmission Data Interrupt Enable bit (TIE) of the DMA/Interrupt

Control Register (SIDICRn) is set.

In addition, DMA transfer is initiated when the Transmission Data DMA Enable bit (TDE) of the

DMA/Interrupt Control Register (SIDICRn) is set.

11.3.6 DMA Transfer

The DMA Request Select field (INTDMA[7:0]) of the Pin Configuration Register (PCFG) can be

used to allocate DMA channels for each reception and transmission channel in the following manner.

SIO Channel 1 Reception

DMA Channel 0

SIO Channel 1 Transmission

DMA Channel 1

SIO Channel 0 Reception

DMA Channel 2

SIO Channel 0 Transmission

DMA Channel 3

Set the DMA Channel Control Register of the DMA Controller as described below.

DMA Request Polarity

Low Active

DMCCRn.ACKPOL = 0

DMA Acknowledge Polarity

Low Active

DMCCRn.REQPOL = 0

Request Detection

Level Detection

DMCCRn.EGREQ = 0

TMPR4937 bảng dữ liệu(PDF) 367 Page - Toshiba Semiconductor

TMPR4937 bảng dữ liệu(HTML) 367 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL