CS4397

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DS333F1

3.0 REGISTER DESCRIPTION

3.1 DIFFERENTIAL DC OFFSET CALIBRATION

Mode Control Register (address 01h)

Access:

Default:

0 - Disabled

Function:

Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be

automatically reset following completion of the calibration sequence.

3.2 SOFT MUTE

Mode Control Register (address 01h)

Access:

Default:

0 - Enabled

Function:

The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-

cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt-

age on the outputs will be retained and MUTEC will go low at the completion of the ramp period.

The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled

state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and

4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE.

76543

210

CAL

MUTE

M4

M3

M2

M1

M0

PDN

CAL

MODE

0

Disabled : CAL complete

1

Enabled : CAL initiated

Table 1.

76543

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CAL

MUTE

M4

M3

M2

M1

M0

PDN

MUTE

MODE

0

Enabled

1

Disabled

Table 2.