TMS320DM355 datasheet(119/153 Pages) TI

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PCLK

(Positive Edge Clocking)

PCLK

(Negative Edge Clocking)

7,9

HD/VD

CI[7:0]/YI[7:0]/

CCD[13:0]

8,10

11,13

12,14

C_WE/C_FIELD

PCLK

(PositiveEdgeClocking)

CI[7:0]/YI[7:0]/

CCD[13:0]

C_WE/C_FIELD

PCLK

(PositiveEdgeClocking)

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing

Table 5-19. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 5-25)

DM355

NO.

UNIT

MIN

MAX

tsu(CCDV-PCLK)

Setup time, CCD valid before PCLK edge

th(PCLK-CCDV)

Hold time, CCD valid after PCLK edge

tsu(CWEV-PCLK)

Setup time, C_WE valid before PCLK edge

th(PCLK-CWEV)

Hold time, C_WE valid after PCLK edge

(1)

The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the

rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.

Figure 5-25. VPFE (CCD) Master Mode Input Data Timing

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