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TMS320DM355 bảng dữ liệu(PDF) 69 Page - Texas Instruments

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tên linh kiện TMS320DM355
Giải thích chi tiết về linh kiện  Digital Media System-on-Chip (DMSoC)
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TMS320DM355 bảng dữ liệu(HTML) 69 Page - Texas Instruments

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TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
Table 3-6. PLL1 Supported Clocking Configurations for DM355 - 270 (24 MHz reference)
PRED
PLLM
POSTDIV
PLL1
ARM /
Peripherals
Venc
VPSS
IV
VCO
MPEG and JPEG
Co-Processor
(/8
(m
(/2 fixed)
(MHz)
PLLDIV1
SYSC
PLLDI
SYSCLK2
PLLDIV3
SYSCLK
PLLDIV4
SYSCLK4
fixed)
programmable)
(/2 fixed)
LK1
V2
(MHz)
(/n
3
(/2 fixed)
(MHz)
(MHz)
(/4
programmable)
(MHz)
fixed)
bypas
bypass
bypass
bypas
2
12
4
6
10
2.4
4
6
s
s
8
180
1
540
2
270
4
135
20
27
4
135
8
171
1
513
2
256.5
4
128.25
19
27
4
128.25
8
162
1
486
2
243
4
121.5
18
27
4
121.5
8
153
1
459
2
229.5
4
114.75
17
27
4
114.75
8
144
1
432
2
216
4
108
16
27
4
108
8
135
1
405
2
202.5
4
101.25
15
27
4
101.25
8
126
1
378
2
189
4
94.5
14
27
4
94.5
8
117
1
351
2
175.5
4
87.75
13
27
4
87.75
8
108
1
324
2
162
4
81
12
27
4
81
8
99
1
297
2
148.5
4
74.25
11
27
4
74.25
8
180
2
270
2
135
4
67.5
10
27
2
135
8
162
2
243
2
121.5
4
60.75
9
27
2
121.5
8
144
2
216
2
108
4
54
8
27
2
108
8
126
2
189
2
94.5
4
47.25
7
27
2
94.5
8
108
2
162
2
81
4
40.5
6
27
2
81
3.5.3.1.2 DM355 - 270 PLL2 (24 MHz reference)
All supported clocking configurations for DM355 - 270 PLL2 with 24 MHz reference clock are shown in
Table 3-3
Table 3-7. PLL2 Supported Clocking Configurations for DM355 - 270 (24 MHz reference)
PREDIV
PLLM
POSTDIV
PLL2 VCO
DDR PHY
DDR Clock
(/n programmable)
(m
(/2 fixed)
(MHz)
PLLDIV1
SYSCLK1
DDR_CLK
programmable)
(/1 fixed)
(MHz)
(MHz)
bypass
bypass
bypass
bypass
1
24
12
8
114
1
342
1
342
171
8
108
1
324
1
324
162
8
102
1
306
1
306
153
8
96
1
288
1
288
144
12
133
1
266
1
266
133
12
100
1
200
1
200
100
15
100
1
160
1
160
80
3.5.3.2 Supported Clocking Configurations for DM355 - 270 (36 MHz reference)
3.5.3.2.1 DM355 - 270 PLL1 (36 MHz reference)
All supported clocking configurations for DM355 - 270 PLL1 with 36 MHz reference clock are shown in
Table 3-4
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Detailed Device Description
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