TMS320DM355 datasheet(87/153 Pages) TI

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TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel

Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event

interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels. The CC

consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering,

channel-chaining, auto-reloading, and memory protection.

The EDMA Channel Controller has the following features:

• Fully orthogonal transfer description

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Three transfer dimensions

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A-synchronized transfers: one dimension serviced per event

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AB- synchronized transfers: two dimensions serviced per event

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Independent indexes on source and destination

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Chaining feature allows 3-D transfer based on single event

• Flexible transfer definition

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Increment and constant addressing modes

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Linking mechanism allows automatic PaRAM set update

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Chaining allows multiple transfers to execute with one event

• Interrupt generation for:

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DMA completion

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Error conditions

• Debug visibility

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Queue watermarking/threshold

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Error and status recording to facilitate debug

• 64 DMA channels

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Event synchronization

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Manual synchronization (CPU(s) write to event set register)

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Chain synchronization (completion of one transfer chains to next)

• 8 QDMA channels

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QDMA channels are triggered automatically upon writing to a PaRAM set entry

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Support for programmable QDMA channel to PaRAM mapping

• 128 PaRAM sets

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Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)

• Two transfer controllers/event queues. The system-level priority of these queues is user programmable

• 16 event entries per event queue

• External events (for example, ASP TX Evt and RX Evt)

The EDMA Transfer Controller has the following features:

• Two transfer controllers

• 64-bit wide read and write ports per channel

• Up to four in-flight transfer requests (TR)

• Programmable priority level

• Supports two dimensional transfers with independent indexes on source and destination (EDMA3CC

manages the 3rd dimension)

• Support for increment and constant addressing modes

• Interrupt and error support

Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in

Parameter RAM (PaRAM) within the CC. DM355 provides 128 PaRAM entries, one for each of the 64

DMA channels and for 64 QDMA / Linked DMA entries.

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