PIC18F44J10-ESLASHML datasheet(148/358 Pages) MICROCHIP

148 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 146

Preliminary

15.3.1

REGISTERS

Each MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register 1 (SSPxCON1)

• MSSP Status Register (SSPxSTAT)

• Serial Receive/Transmit Buffer Register

(SSPxBUF)

• MSSP Shift Register (SSPxSR) – Not directly

accessible

SSPxCON1 and SSPxSTAT are the control and status

registers in SPI mode operation. The SSPxCON1

the SSPxSTAT are read-only. The upper two bits of the

SSPxSTAT are read/write.

SSPxSR is the shift register used for shifting data in or

out. SSPxBUF is the buffer register to which data

bytes are written to or read from.

receive

operations,

SSPxSR

and

SSPxBUF

together create a double-buffered receiver. When

SSPxSR receives a complete byte, it is transferred to

SSPxBUF and the SSPxIF interrupt is set.

During

transmission,

the

SSPxBUF

not

double-buffered. A write to SSPxBUF will write to both

SSPxBUF and SSPxSR.

SSPxSTAT: MSSPx STATUS REGISTER (SPI™ MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Sample bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit

= Transmit occurs on transition from active to Idle clock state

= Transmit occurs on transition from Idle to active clock state

Note:

Polarity of clock state is set by the CKP bit (SSPxCON1<4>).

bit 5

D/A: Data/Address bit

Used in I2C mode only.

bit 4

P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

S: Start bit

Used in I2C mode only.

bit 2

R/W: Read/Write Information bit

Used in I2C mode only.

bit 1

UA: Update Address bit

Used in I2C mode only.

bit 0

BF: Buffer Full Status bit (Receive mode only)

= Receive complete, SSPxBUF is full

= Receive not complete, SSPxBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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