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PIC18F44J10-E/ML bảng dữ liệu(PDF) 118 Page - Microchip Technology

tên linh kiện PIC18F44J10-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 118 Page - Microchip Technology

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PIC18F45J10 FAMILY
DS39682C-page 116
Preliminary
© 2007 Microchip Technology Inc.
11.1
Timer1 Operation
Timer1 can operate in one of these modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is
enabled, the RC1/T1OSI and
RC0/T1OSO/T1CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 11-1:
TIMER1 BLOCK DIAGRAM
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T1CKI
T1OSI
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T1CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input



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