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PIC18F44J10-E/ML bảng dữ liệu(PDF) 108 Page - Microchip Technology |
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PIC18F44J10-E/ML bảng dữ liệu(HTML) 108 Page - Microchip Technology |
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108 / 358 page ![]() PIC18F45J10 FAMILY DS39682C-page 106 Preliminary © 2007 Microchip Technology Inc. 9.6 PORTE, TRISE and LATE Registers Depending on the particular PIC18F45J10 family device selected, PORTE is implemented in two different ways. For 40/44-pin devices, PORTE is a 4-bit wide port. Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as analog inputs, these pins will read as ‘0’s. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. The upper four bits of the TRISE register also control the operation of the Parallel Slave Port. Their operation is explained in Register 9-1. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. EXAMPLE 9-6: INITIALIZING PORTE Note: PORTE is only available in 40/44-pin devices. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs. CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0Ah ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs |
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