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PIC18F44J10-E/ML bảng dữ liệu(PDF) 103 Page - Microchip Technology

tên linh kiện PIC18F44J10-E/ML
Giải thích chi tiết về linh kiện  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
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© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 101
PIC18F45J10 FAMILY
TABLE 9-7:
PORTC I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/T1OSO/
T1CKI
RC0
0
O
DIG
LATC<0> data output.
1
I
ST
PORTC<0> data input.
T1OSO
x
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T1CKI
1
I
ST
Timer1 counter input.
RC1/T1OSI/CCP2
RC1
0
O
DIG
LATC<1> data output.
1
I
ST
PORTC<1> data input.
T1OSI
x
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1)
0
O
DIG
CCP2 compare and PWM output; takes priority over port data.
1
I
ST
CCP2 capture input.
RC2/CCP1/P1A
RC2
0
O
DIG
LATC<2> data output.
1
I
ST
PORTC<2> data input.
CCP1
0
O
DIG
ECCP1/CCP1 compare or PWM output; takes priority over port data.
1
I
ST
ECCP1/CCP1 capture input.
P1A(2)
0
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK1/SCL1
RC3
0
O
DIG
LATC<3> data output.
1
I
ST
PORTC<3> data input.
SCK1
0
O
DIG
SPI™ clock output (MSSP1 module); takes priority over port data.
1
I
ST
SPI clock input (MSSP1 module).
SCL1
0
ODIG
I2C™ clock output (MSSP1 module); takes priority over port data.
1
II2C/SMB I2C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/SDA1
RC4
0
O
DIG
LATC<4> data output.
1
I
ST
PORTC<4> data input.
SDI1
1
I
ST
SPI data input (MSSP1 module).
SDA1
1
ODIG
I2C data output (MSSP1 module); takes priority over port data.
1
II2C/SMB I2C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC5
0
O
DIG
LATC<5> data output.
1
I
ST
PORTC<5> data input.
SDO1
0
O
DIG
SPI data output (MSSP1 module); takes priority over port data.
RC6/TX/CK
RC6
0
O
DIG
LATC<6> data output.
1
I
ST
PORTC<6> data input.
TX
1
O
DIG
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
CK
1
O
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
I
ST
Synchronous serial clock input (EUSART module).
RC7/RX/DT
RC7
0
O
DIG
LATC<7> data output.
1
I
ST
PORTC<7> data input.
RX
1
I
ST
Asynchronous serial receive data input (EUSART module).
DT
1
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must
configure as an input.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note
1:
Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
2:
Enhanced PWM output is available only on PIC18F44J10/45J10 devices.



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