PIC18F44J10-ESLASHML datasheet(266/358 Pages) MICROCHIP

266 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 264

Preliminary

IORLW

Inclusive OR Literal with W

Syntax:

IORLW k

Operands:

≤ k ≤ 255

Operation:

(W) .OR. k

→ W

Status Affected:

N, Z

Encoding:

0000

1001

kkkk

Description:

The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

IORLW

35h

Before Instruction

9Ah

After Instruction

BFh

IORWF

Inclusive OR W with f

Syntax:

IORWF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) .OR. (f)

→ dest

Status Affected:

N, Z

Encoding:

0001

00da

ffff

Description:

Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

IORWF

RESULT, 0, 1

Before Instruction

RESULT =

13h

91h

After Instruction

RESULT =

13h

93h

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