PIC18F44J10-ESLASHML datasheet(215/358 Pages) MICROCHIP

215 / 358 page

Preliminary

DS39682C-page 213

PIC18F45J10 FAMILY

The value in the ADRESH:ADRESL registers is not

modified for a Power-on Reset. The ADRESH:ADRESL

registers will contain unknown data after a Power-on

Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 17.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur between setting the GO/DONE bit and the actual

start of the conversion.

The following steps should be followed to perform an A/D

conversion:

Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

Wait the required acquisition time (if required).

Start conversion:

• Set GO/DONE bit (ADCON0 register)

Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF, if required.

For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 17-2:

A/D TRANSFER FUNCTION

FIGURE 17-3:

ANALOG INPUT MODEL

3FEh

003h

002h

001h

000h

Analog Input Voltage

3FFh

VAIN

CPIN

ANx

5 pF

VT = 0.6V

ILEAKAGE

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD = 25 pF

VSS

VDD

± 100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch Resistance

RSS

VDD

Sampling Switch

Ω)

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