PIC18F44J10-ESLASHML datasheet(208/358 Pages) MICROCHIP

208 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 206

Preliminary

16.4

EUSART Synchronous

Slave Mode

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is sup-

plied externally at the CK pin (instead of being supplied

internally in Master mode). This allows the device to

transfer or receive data while in any low-power mode.

16.4.1

EUSART SYNCHRONOUS

SLAVE TRANSMISSION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the

TSR register and transmit.

The second word will remain in the TXREG

Flag bit, TXIF, will not be set.

When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit, TXIF, will now be

set.

If enable bit TXIE is set, the interrupt will wake the

chip from Sleep. If the global interrupt is enabled,

the program will branch to the interrupt vector.

To set up a Synchronous Slave Transmission:

Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 16-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSP1IF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

TXREG

EUSART Transmit Register

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

BAUDCON

ABDOVF

RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

SPBRGH

EUSART Baud Rate Generator Register High Byte

SPBRG

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Note 1:

These bits are not implemented on 28-pin devices and should be read as ‘0’.

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