LTC2414IGN datasheet(24/48 Pages) LINER

24 / 48 page

LTC2414/LTC2418

241418fa

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

then immediately begins outputting data. The data input/

output cycle begins on the first rising edge of SCK and

ends after the 32nd rising edge. The input data is then

shifted in via the SDI pin on the rising edge of SCK

(including the first rising edge) and the output data is

shifted out of the SDO pin on each falling edge of SCK.

The internally generated serial clock is output to the SCK

pin. This signal may be used to shift the conversion result

into external circuitry. EOC can be latched on the first

rising edge of SCK and the last bit of the conversion result

can be latched on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1) indicating a

new conversion is in progress. SCK remains HIGH during

the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2414/LTC2418 are designed to reduce as much as

possible the conversion result sensitivity to device

decoupling, PCB layout, antialiasing circuits, line fre-

quency perturbations and so on. Nevertheless, in order to

preserve the extreme accuracy capability of this part,

some simple precautions are desirable.

Digital Signal Levels

The LTC2414/LTC2418’s digital interface is easy to use.

Its digital inputs (SDI, FO,CSandSCKinExternalSCKmode

of operation) accept standard TTL/CMOS logic levels and

the internal hysteresis receivers can tolerate edge rates as

slow as 100

µs.However,someconsiderationsarerequired

to take advantage of the exceptional accuracy and low

supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

While a digital input signal is in the range 0.5V to

(VCC – 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (SDI, FO, CS and

SCK in External SCK mode of operation) is within this

range, the power supply current may increase even if the

signal in question is at a valid logic level. For micropower

APPLICATIO S I FOR ATIO

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

(1)

(0)

SGL

ODD/

SIGN

SDI

DON’T CARE

SDO

SCK

(INTERNAL)

LSB

MSB

SIG

BIT 6

BIT 0

PARITY

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

DATA OUTPUT

CONVERSION

241418 F10

VCC

REF+

REF–

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

919

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

µF

2.7V TO 5.5V

LTC2414/

LTC2418

3-WIRE

SPI INTERFACE

•

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