LTC2414IGN datasheet(13/48 Pages) LINER

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LTC2414/LTC2418

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specification for the REF+ and REF– pins covers the entire

range from GND to VCC. For correct converter operation,

the REF+ pin must always be more positive than the REF–

pin.

The LTC2414/LTC2418 can accept a differential reference

voltage from 0.1V to VCC. The converter output noise is

determined by the thermal noise of the front-end circuits,

and, as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

significantly improve the converter’s effective resolution.

On the other hand, a reduced reference voltage will im-

prove the converter’s overall INL performance. A reduced

reference voltage will also improve the converter perfor-

mance when operated with an external conversion clock

(external FOsignal)atsubstantiallyhigheroutputdatarates.

Input Voltage Range

The two selected pins are labeled IN+ and IN– (see Tables

1 and 2). Once selected (either differential or single-ended

multiplexing mode), the analog input is differential with a

common mode range for the IN+ and IN– input pins ex-

tending from GND – 0.3V to VCC + 0.3V. Outside

these limits, the ESD protection devices begin to turn on

and the errors due to input leakage current increase rap-

idly. Within these limits, the LTC2414/LTC2418 convert

the bipolar differential input signal, VIN = IN+ – IN–, from

– FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF =

REF+ – REF –. Outside this range the converters indicate

the overrange or the underrange condition using distinct

output codes.

Input signals applied to IN+ and IN– pins may extend

300mV below ground or above VCC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN+ or IN– pins without affecting the performance

of the device. In the physical layout, it is important to

maintain the parasitic capacitance of the connection be-

tween these series resistors and the corresponding pins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. In addition, series

resistors will introduce a temperature dependent offset

error due to the input leakage current. A 1nA input leakage

current will develop a 1ppm offset error on a 5k resistor if

VREF = 5V. This error has a very strong temperature

dependency.

Input Data Format

When the LTC2414/LTC2418 are powered up, the default

selection used for the first conversion is IN+ = CH0 and IN–

= CH1 (Address = 00000). In the data input/output mode

following the first conversion, a channel selection can be

updated using an 8-bit word. The LTC2414/LTC2418

serial input data is clocked into the SDI pin on the rising

edge of SCK (see Figure 3). The input is composed of an

8-bit word with the first 3 bits acting as control bits and the

remaining 5 bits as the channel address bits.

The first 2 bits are always 10 for proper updating opera-

tion. The third bit is EN. For EN = 1, the following 5 bits are

used to update the input channel selection. For EN = 0,

previous channel selection is kept and the following bits

are ignored. Therefore, the address is updated when the 3

control bits are 101 and kept for 100. Alternatively, the 3

control bits can be all zero to keep the previous address.

This alternation is intended to simplify the SDI interface

allowing the user to simply connect SDI to ground if no

update is needed. Combinations other than 101, 100 and

000 of the 3 control bits should be avoided.

When update operation is set (101), the following 5 bits

are the channel address. The first bit, SGL, decides if the

differential selection mode (SGL = 0) or the single-ended

selection mode is used (SGL = 1). For SGL = 0, two

adjacent channels can be selected to form a differential

input; for SGL = 1, one of the 8 channels (CH0-CH7) for the

LTC2414 or one of the 16 channels (CH0-CH15) for the

LTC2418 is selected as the positive input and the COM pin

is used as the negative input. For the LTC2414, the lower

half channels (CH0-CH7) are used and the channel ad-

dress bit A2 should be always 0, see Table 1. While for the

LTC2418, all the 16 channels are used and the size of the

corresponding selection table (Table 2) is doubled from

that of the LTC2414 (Table 1). For a given channel selec-

tion, the converter will measure the voltage between the

two channels indicated by IN+ and IN– in the selected row

of Tables 1 or 2.

APPLICATIO S I FOR ATIO

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