LTC2414IGN datasheet(22/48 Pages) LINER

22 / 48 page

LTC2414/LTC2418

241418fa

When testing EOC, if the conversion is complete (EOC = 0),

the device will exit the low power mode during the EOC

test. In order to allow the device to return to the low power

sleep state, CS must be pulled HIGH before the first rising

edge of SCK. In the internal SCK timing mode, SCK goes

HIGH and the device begins outputting data at time tEOCtest

after the falling edge of CS (if EOC = 0) or tEOCtest after EOC

goes LOW (if CS is LOW during the falling edge of EOC).

The value of tEOCtest is 23µs if the device is using its internal

oscillator (FO = logic LOW or HIGH). If FO is driven by an

external oscillator of frequency fEOSC, then tEOCtest is

3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the

device returns to the sleep state and the conversion result

is held in the internal static shift register.

If CS remains LOW longer than tEOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shifted out of the SDO pin. The data I/O cycle concludes

after the 32nd rising edge. The input data is then shifted in

via the SDI pin on the rising edge of SCK (including the first

rising edge) and the output data is shifted out of the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

EOC can be latched on the first rising edge of SCK and the

last bit of the conversion result on the 32nd rising edge of

SCK. After the 32nd rising edge, SDO goes HIGH (EOC =

1), SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. If the device has not finished loading the

last input bit A0 of SDI by the time CS is pulled HIGH, the

address information is discarded and the previous ad-

dress is still kept. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

the SCK pin or by never pulling CS HIGH when SCK is LOW.

APPLICATIO S I FOR ATIO

Figure 8. Internal Serial Clock, Single Cycle Operation

(1)

(0)

SGL

ODD/

SIGN

SDI

DON’T CARE

SDO

SCK

(INTERNAL)

MSB

SIG

BIT 0

LSB

PARITY

BIT 6

TEST EOC

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

241418 F08

<tEOCtest

Hi-Z

TEST EOC

VCC

REF+

REF–

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

919

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

µF

2.7V TO 5.5V

LTC2414/

LTC2418

4-WIRE

SPI INTERFACE

•

VCC

10k

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