AMD-K6-2ESLASH233AMZ datasheet(191/332 Pages) AMD

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Chapter 6

Bus Cycles

173

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Stop Grant and Stop

Clock States

Figure 71 on page 174 and Figure 72 on page 175 show the

processor transition from normal execution to the Stop Grant

state, then to the Stop Clock state, back to the Stop Grant state,

and finally back to normal execution. The series of transitions

begins when the processor samples STPCLK# asserted. On

recognizing a STPCLK# interrupt at the next instruction

retirement boundary, the processor performs the following

actions, in the order shown:

1. Its instruction pipelines are flushed.

2. All pending and in-progress bus cycles are completed.

3. The STPCLK# assertion is acknowledged by executing a

Stop Grant special bus cycle.

4. Its internal clock is stopped after BRDY# of the Stop Grant

special bus cycle is sampled asserted and after EWBE# is

sampled asserted (if EWBE# is masked off, then entry into

the Stop Grant state is not affected by EWBE#).

5. The Stop Clock state is entered if the system logic stops the

bus clock CLK (optional).

STPCLK# is sampled as a level-sensitive input on every clock

edge but is not recognized until the next instruction boundary.

The system logic drives the signal either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks. STPCLK#

must remain asserted until recognized, which is indicated by

the completion of the Stop Grant special cycle.

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