S32K311NHT0MPAST datasheet(120/143 Pages) NXP

120 / 143 page

Table 66. JTAG electrical specifications (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tTDOHZ

TCK low to TDO

high impedance

—

tBSDV

TCK falling edge to

output valid 4

—

600

—

tBSDVZ

TCK falling edge to

output valid out of

high impedance

—

600

—

tBSDHZ

TCK falling edge

to output high

impedance

—

600

—

tBSDST

Boundary scan input

valid to TCK rising

edge

—

tBSDHT

TCK rising edge to

boundary scan input

invalid

—

1. Cycle time is 30ns assuming full cycle timing. Cycle time is 60ns assuming half cycle timing.

2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.

Refer to pad specification for allowed transition frequency

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

TCK

Figure 65. JTAG TCK Input Timing

NXP Semiconductors

Debug modules

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

120 / 143

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