S32K311NHT0MPAST datasheet(53/143 Pages) NXP

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Table 17. RUN mode supply currents (peripherals disabled) for S32K3x8, S32K34x, S32K32x and S32K314 (continued)

S32K344,

S32K324,

S32K314

25, typ 7

51.3

54.8

69.6

62.7

75.1

97.5

0.6

3.1

25, max 8

60.2

64.5

80.4

73.3

86.8

110

0.8

3.6

85, typ 7

64.5

68.1

83.1

76.2

111

0.6

3.2

85, max 8

104

108

124

117

131

155

0.8

3.9

105, typ 7

75.4

93.9

87.3

100

122.6

0.6

3.2

105, max 8

145

149

166

159

173

197

0.8

4.0

125, typ 7

97.4

101.2

116.4

110

122.9

145.7

0.6

3.3

125, max 8, 9

191

196

212

206

220

245

0.8

4.3

S32K342,

S32K322,

S32K341

25, typ 7

49.5

52.2

66.3

58.9

72.7

93.7

0.5

3.0

25, max 8

58.5

62.4

75.9

68.1

82.9

104.6

0.8

3.6

85, typ 7

58.6

63.6

75.7

67.9

82.3

106.1

0.5

3.0

85, max 8

89.6

102.3

110.8

105.4

124.1

155

0.8

3.8

105, typ 7

68.3

85.6

92.3

119.3

0.5

3.1

105, max 8

124

143.4

157.5

150.5

164.5

191.6

0.8

4.0

125, typ 7

79.8

85.1

97.1

89.1

103.8

140.1

0.5

3.2

125, max 8, 9 146.7

164.7

178

171.3

188.7

235.6

0.8

4.2

1. Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.

2. See the configurations in Table 22.

3. RUN IDD @ V15 includes Flash memory read current from the V11 voltage rail.

4. For S32K388, the current from a V15 supply will flow through the external NMOS for the V11 regulation stage, and into the

V11 pins of the device.

5. IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the

application.

6. RUN IDD @ VDD_HV_A includes Flash memory read current from the V25 voltage rail.

7. “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A =

5.0V, VDD_HV_B = 5.0V, V15 = 1.5V, for the typical silicon process.

8. "max" is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V),

VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, V15= 1.65V, for the fast silicon process.

9. For the maximum allowable RUN current in an application, the junction temperature must be kept below the maximum

specification, TJ < 150°C, to avoid self-heating.

The data in this table is preliminary and based on first samples.

NOTE

Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user

configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the

device), temperature = 25 °C and typical silicon process unless otherwise stated.

NXP Semiconductors

Power management

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

53 / 143

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