Datasheet

15

002-37178 Rev. *B

2023-10-10

EZ-PD™ PAG2S-PS integrated USB PD and

synchronous-rectification controller

Functional description

3.2

Fault protection

3.2.1

VBUS OVP, UVP, OCP, and SCP

VBUS undervoltage and overvoltage faults are monitored using internal VBUS_IN/VBUS_C resistor dividers. VBUS

overcurrent and short-circuit faults are monitored using internal current sense amplifiers. The fault thresholds

and response mechanisms are firmware configurable.

3.2.2

OTP

Over-temperature monitoring is done using an external thermistor and internal ADC. The thermistor can be

connected to any free GPIO. EZ-PD™ PAG2S-PS has integrated 8-bit SAR ADC, this is available for general purpose

analog to digital conversions. The fault thresholds and response mechanisms are firmware configurable.

3.2.3

ESD, CC OVP, and DP/DM OVP

EZ-PD™ PAG2S-PS offers ESD protection on all the pins. Further, the chip integrates protection against accidental

short of CC pins to high voltage VBUS_C rail and also protects against over-voltage on DP/DM pins.

3.3

Power modes

EZ-PD™ PAG2S-PS supports multiple power modes - Active, Sleep, and DeepSleep. Transitions between these

modes is handled by the application firmware depending on the operating conditions.

3.4

MCU subsystem

EZ-PD™ PAG2S-PS integrates a 32-bit Cortex®-M0+ MCU with 64KB flash, 8 KB SRAM, and 64 KB ROM. EZ-PD™

PAG2S-PS also supports 1x TCPWM and 2x ADC.