Datasheet

10

002-37178 Rev. *B

2023-10-10

EZ-PD™ PAG2S-PS integrated USB PD and

synchronous-rectification controller

Pinouts

2.2.6

CC1, CC2

CC1 and CC2 are the communication channels for the USB PD protocol. EZ-PD™ PAG2S-PS integrates a USB PD

transceiver consisting of a transmitter (TX) and receiver (RX) that communicate Biphase Mark Code (BMC)

encoded data over the Configuration Channel (CC) channels as per the USB PD standard. All communication is

half-duplex. The physical layer implements collision avoidance to minimize communication errors on the

channel. This block includes all termination resistors (Rp) and their switches as required by the USB PD

specification.

To support active cable applications, EZ-PD™ PAG2S-PS also integrates VCONN FETs to power CC lines. An

external 390-pF capacitor is required on both the CC1 and CC2 pins.

2.2.7

DP_GPIOx, DM_GPIOx

The DP and DM lines are the standard USB D+ and D– lines. EZ-PD™ PAG2S-PS integrates a charge detect block,

which handles legacy charging protocols such as BC 1.2, Quick Charge, Apple Charging, and Samsung AFC. This

block integrates all the terminations required for these charging protocols and no external components are

required. When legacy charging is not required in the system, the same DP and DM lines can be re-used as

standard GPIOs. Charger detect block also supports impedance detection on DP/DM lines.

2.2.8

GPIOx, XRES

EZ-PD™ PAG2S-PS has multiple GPIOs, out of which some are dedicated GPIOs and the rest are multiplexed with

other functionalities. These GPIOs support multiple drive modes and configurable threshold options. During

power-on and reset, the GPIOs are forced to the tristate so as not to crowbar any inputs and/or cause excess

turn-on current.

The XRES pin can be used to initiate a reset, this pin is internally pulled high and needs to be pulled low externally

to trigger a reset.