VC0736 datasheet(99/127 Pages) NEXTCHIP

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NVP6124

Data sheet

02.11.2015 (REV 0.2)

97/125

4-CH AHD2.0 RX and 9-CH Audio Codec



Registers to Control Audio Interface

ADDRESS

BITS

VALUE

DESCRIPTION

Bank

Addr

30P

25P

0x0E

R_SEQ_09[4]

[0]

0x0

R_SEQ

: Sequence of Audio Data for

ADATA_REC

00000

channel 1 data

00001

channel 2 data

00010

channel 3 data

00011

channel 4 data

00100

channel 5 data

00101

channel 6 data

00110

channel 7 data

00111

channel 8 data

01000

channel 9 data

01001

channel 10 data

01010

channel 11 data

01011

channel 12 data

01100

channel 13 data

01101

channel 14 data

01110

channel 15 data

01111

channel 16 data

10000

Mic input 1

10001

Mic input 2

R_SEQ_10[4]

[1]

0x0

R_SEQ_11[4]

[2]

0x0

R_SEQ_12[4]

[3]

0x0

R_SEQ_13[4]

[4]

0x0

R_SEQ_14[4]

[5]

0x0

R_SEQ_15[4]

[6]

0x0

R_SEQ_16[4]

[7]

0x0

0x0F

R_SEQ_09

[3:0]

0x98

R_SEQ_10

[7:4]

0x10

R_SEQ_11

[3:0]

0xBA

R_SEQ_12

[7:4]

0x11

R_SEQ_13

[3:0]

0xDC

R_SEQ_14

[7:4]

0x12

R_SEQ_15

[3:0]

0xFE

R_SEQ_16

[7:4]

0x3C

MIC_SEQ_01

[4:0]

0x00

0x3D

MIC_SEQ_02

[4:0]

0x00



Registers to Control Audio Interface

ADDRESS

BITS

VALUE

DESCRIPTION

Bank

Addr

30P

25P

0x13

PB_MASTER

[7]

0x08

PB_MASTER

: Selection of master & slave mode of ACLK_PB and ASYNC_PB

Slave mode

Master mode

PB_CLK

[6]

PB_CLK

: Set the relationship between audio signal outputted to ADATA_PB and

clock outputted to ACLK_PB

inverted clock

non-inverted clock

PB_BITRATE

[5:4]

PB_BITRATE

: Set the bit rate of audio signal outputted to ADATA_PB

256fs

320fs

384fs

PB_SAMRATE

[3]

PB_SAMRATE

: Set the sampling rate of data outputted to ADATA_PB

8KHz

16KHz

PB_BITWID

[2]

PB_BITWID

: Set the bit width of data outputted to ADATA_PB

16bits

8bits

PB_SSP

[1]

PB_SSP

: Set the position of data and sync signals inputted to ADATA_PB, when

ASYNC_PB is DSP mode.

DSP mode

SSP mode

PB_SYNC

[0]

PB_SYNC

: Set the sync's mode inputted/outputted to ASYNC_PB.

I2S mode

DSP mode

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